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toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 1 tentative toshiba mos digital inte grated circuit silicon gate cmos 32 gbit (4g 8 bit) cmos nand e 2 prom (multi-level-cell) description the tc58nvg5d2 is a single 3.3 v 32 gbit (36,274,176, 000 bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (8192 + 448) bytes 128 pages 4100 blocks. the device has two 8640-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8640-byte increments. the erase operation is implemented in a single block unit (1 mbytes + 56 kbytes: 8640 bytes 128 pages). the tc58nvg5d2 is a serial-type memory device whic h utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. features ? organization tc58nvg5d2f memory cell array 8640 512k 8 register 8640 8 page size 8640 bytes block size (1m + 56 k) bytes ? modes read, reset, auto page program, auto block erase, status read, page copy, multi page program, multi block erase, multi page copy, mullti page read ? mode control serial input/output command control ? number of valid blocks min 3936 blocks max 4100 blocks ? power supply v cc = 2.7 v to 3.6 v ? access time cell array to register 200 s max serial read cycle 25 ns min ? program/erase time auto page program 1600 s/page typ. auto block erase 4 ms/block typ. ? operating current read (25 ns cycle) tbd ( 50 ma max.) program (avg.) tbd ( 50 ma max.) erase (avg.) tbd ( 50 ma max.) standby 100 a max ? package (weight: tbd g typ.) ? for reliability guidance, please refer to the application notes and comments (17). 24 bit ecc for each 1024 bytes is required. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 2 pin assignment (top view) pin names i/o1 ~ i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable psl power on select wp write protect by / ry ready/busy v cc power supply v ccq i/o port powe supply v ss ground n.c no connection vss nc nc nc i/o8 i/o7 i/o6 i/o5 nc psl vccq v cc v ss nc vccq nc i/o4 i/o3 i/o2 i/o1 nc nc nc vss 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 vcc vss nc nc nc nc by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc vss vcc 8 8 TC58NVG5D2FTA00 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 v to v cc + 0.3 v ( 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature -55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta = 25c, f = 1 mhz) symb0l parameter condition min max unit c in input v in = 0 v ? 10 pf c out output v out = 0 v ? 10 pf * this parameter is periodically samp led and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry v cc i/o1 v ss i/o8 psl ce cle ale we re by / ry row address buffer decoder to wp address register free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 4 valid blocks symbol parameter min typ. max unit n vb number of valid blocks 3936 ? 4100 blocks note: the device occasionally contains unus able blocks. refer to application note (13) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over the device lifetime. * the number of valid blocks includes extended blocks. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 v ? 3.6 v v v ih high level input voltage 2.7 v v cc 3.6 v 0.8 x vcc ? v cc + 0.3 v v il low level input voltage 2.7 v v cc 3.6 v ? 0.3 * ? 0.2 x vcc v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v to v cc ? ? 10 a i lo output leakage current v out = 0 v to v cc ? ? 10 a psl = gnd or nu ? ? tbd i cco0 * power on reset current psl = v cc , ffh command input after power on ? ? tbd ma i cco1 serial read current ce = v il , i out = 0 ma, tcycle = 30 ns ? ? tbd ma i cco2 programming current ? ? ? tbd ma i cco3 erasing current ? ? ? tbd ma i ccs standby current ce = v cc ? 0.2 v, wp = 0 v/v cc , psl = 0 v/v cc /nu ? ? 100 a v oh high level output voltage i oh = ? 0.4 ma (2.7 v v cc 3.6 v) 2.4 ? ? v v ol low level output voltage i ol = 2.1 ma (2.7 v v cc 3.6 v) ? ? 0.4 v i ol ( by / ry ) output current of by / ry pin v ol = 0.4 v (2.7 v v cc 3.6 v) ? 8 ? ma * refer to application note (2) for detail free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 5 ac characteristics and recommended operating conditions (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter min max unit t cls cle setup time 0 ? ns t cls2 cle setup time 30 ? ns t clh cle hold time 5 ? ns t cs ce setup time 8 ? ns t cs2 ce setup time 20 ? ns t ch ce hold time 5 ? ns t wp write pulse width 12 ? ns t als ale setup time 0 ? ns t alh ale hold time 5 ? ns t ds data setup time 10 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t whw * we high hold time from final address to first data 120 ? ns t ww wp high to we low 100 ? ns t rr ready to re falling edge 20 ? ns t rw ready to we falling edge 20 ? ns t rp read pulse width 12 ? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns t cr ce low to re low 10 ? ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rhoh data output hold time from re high 25 ? ns t rloh data output hold time from re low 5 ? ns t rhz re high to output high impedance ? 60 ns t chz ce high to output high impedance ? 30 ns t clhz cle high to output high impedance ? 30 ns t reh re high hold time 10 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr1 we high to re low (status read) 180 ? ns t whr2 we high to re low (column address change in read) 300 ? ns t r memory cell array to starting address ? 200 s t dcbsyr1 data cache busy in read cache (following 31h and 3fh) ? 200 s t dcbsyr2 data cache busy in page copy (following 3ah) ? 205 s t wb we high to busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 10/10/30/500 s * twhw is the time from the we rising edge of final address cycle to the we falling edge of first data cycle. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 6 ac test conditions condition parameter 2.7 v v cc 3.6 v input level 0 v to v cc input pulse rise and fall time 3ns input comparison level v cc /2 output data comparison level v cc /2 output load c l (50 pf) + 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by / ry pin. (refer to application note (9) toward the end of this document.) programming and erasing characteristics (ta = 0 to 70 ? , v cc = 2.7 v to 3.6 v) symbol parameter min typ. max unit notes t prog average programming time ? 1600 3000 s t dcbsyw1 data cache busy time in write cache (following 11h) ? ? 10 s t dcbsyw2 data cache busy time in write cache (following 15h) ? ? 3000 s (2) n number of partial program cycles in the same page ? ? ? (1) t berase block erasing time ? 4 10 ms (1) refer to application note (12) toward the end of this document. (2) t dcbsyw2 depends on the timing between internal programming time and data in time. data output when treh is long, output buffers are disabled by / re=high, and the hold time of data output depend on trhoh (25 ns min). on this condition, wa veforms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and the hold time of data output depend on trloh (5ns min). on this condition, output buffers are disabled by the rising edge of cle, ale, /ce or falling edge of /we, and waveforms look like extended data output mode. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 7 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce we hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 8 address input cycle timing diagram data input cycle timing diagram pa16 to 19 pa8 to 15 ca8 to 13 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t cs ce we ale i/o t dh t ds t wp t wh t dh t ds t wp t wh t wc t dh t ds t wp t wh t wc pa0 to 7 t clh t ch t ch : v ih or v il we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o d in 8639 * t dh t ds t dh t ds t cs t cls t ch t cs t alh free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 9 serial read cycle timing diagram status read cycle timing diagram t whr1 we t dh t ds t cls t clr t cs t clh t ch t wp status output 70h * t whc t cr t ir t rea t rhz t chz ce cle re by / ry i/o : v ih or v il t rhoh * : 70h represents the hexadecimal number t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o t rhoh t rhoh t rhoh t rp t rp t rp t cr t cr free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 10 read cycle timing diagram read cycle timing diagram: when interrupted by ce 30h pa16 to 19 pa8 to 15 pa0 to 7 ca8 to 13 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea t cr col. add. n t dh t ds 00h d out n d out n + 1 by / ry t chz t rhz t rhoh col. add. n 30h pa16 to 19 pa8 to 15 pa0 to 7 ca8 to 13 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea t cr col. add. n data out from col. add. n t dh t ds 00h d out n d out n + 1 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 11 read cycle with data cache timing diagram (1/2) 30h pa16 to 19 pa8 to 15 pa0 to 7 ca8 to 13 ca0 to 7 i/o t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea column address n * t dh t ds 00h d out 0 d out 1 by / ry t cr page address m d out 31h t dh t ds t wb t dcbsyr1 31h t dh t ds t wb d out 0 t rr t rea t dcbsyr1 t cs t cls t clh t ch t clr t cs t cls t clh t ch t clr t cr page address m col. add. 0 col. add. 0 page address m + 1 t rw t cs t cls t clh t ch 1 continues to of next page 1 * the column address will be reset to 0 by the 31h command input. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 12 read cycle with data cache timing diagram (2/2) continues from of last page 1 i/o we cle ce ale re by / ry d out t clr t wb 31h t dh t ds t cs t cls t clh t ch t wb 31h t dh t ds t cs t cls t clh t ch t rc t rr t rea page address m + 1 page address m + x t clr t wb t rc t rr t rea t cr 3fh t dh t ds t cs t cls t clh t ch d out 0 d out 1 d out t rc t rr t rea t cr page address m + 2 t dcbsyr1 t dcbsyr1 t dcbsyr1 t clr col. add. 0 col. add. 0 col. add. 0 t cr d out 0 d out 1 d out d out 0 d out 1 d out 1 (note) make sure to terminat e the operation with 3fh command. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 13 column address change in read cycle timing diagram (1/2) t clr i/o t cs t cls t clh t ch t wc t als t alh t r cle ce ale re t dh t ds t dh t ds column address a t alh t wb t cs t cls t clh t ch t als t rc t rea t cr t rr page address p page address p column address a 00h ca0 to 7 t dh t ds ca8 to 13 t dh t ds pa0 to 7 t dh t ds pa8 to 15 t dh t ds pa16 to 19 t dh t ds 30h d out a d out a + 1 d out a + n we 1 continues from of next page 1 by / ry free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 14 column address change in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 13 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a + n t rhw page address p column address b t rc t clr t cr t ir d out b + n? d out b + 1 d out b 1 continues from of last page 1 we by / ry t whr2 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 15 data output timing diagram t reh t rea t rc t rr t rloh t rea re by / ry i/o t rea t rp t rp t rp t rloh we cle ce ale t cls2 t clh t chz t cs2 t clhz low t dh t ds command dout dout dout t cr t rhz t rhoh free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 16 auto-program operation timing diagram ca0 to 7 t cls t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t prog t wb t ds t alh t als * ) m: up to 8567 column address n ca8 to 13 d in n d in m 10h 70h status output pa0 to 7 pa8 to 15 pa16 to 19 80h d in n+1 t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 17 auto-program operation with data cache timing diagram (1/3) t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw2 d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 8639 1 continues to 1 of next page pa16 to 19 ca0 to ca12 is 0 in this diagram. ca0 to 7 ca0 to 7 ca8 to 13 pa0 to 7 pa8 to 15 t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 18 auto-program operation with data cache timing diagram (2/3) t cls t als t ds t dh ca0 to 7 80h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 13 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw2 d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 8639 pa16 to 19 2 pa8 to 15 ca0 to 7 repeat a max of 126 times (in order to program pages 1 to 126 of a block). t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 19 auto-program operation with data cache timing diagram (3/3) 70h t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 2 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 8639 continued from 2 of last page ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is t prog max. 80h ca0 to 7 ca8 to 13 pa0 to 7 pa8 to 15 pa16 to 19 d in 0 d in 1 10h status t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 20 multi-page program operation with data cache timing diagram (1/4) continues to 1 of next page t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw1 d in 0 d in 1 t wb 80h t ds 11h t alh t als d in 8639 1 pa16 to 19 ca0 to 7 ca0 to 7 ca8 to 13 pa0 to 7 pa8 to 15 page address m district-0 t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 21 multi-page program operation with data cache timing diagram (2/4) t cls t als t ds t dh ca0 to 7 80h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 13 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw2 d in 0 d in 1 t wb 80h t ds 15h t alh t als d in 8639 pa16 to 19 2 pa8 to 15 ca0 to 7 repeat a max of 127 times (in order to program pages 0 to 126 of a block). page address m district-1 t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 22 multi-page program operation with data cache timing diagram (3/4) i/o t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw1 d in 0 d in 1 t wb 80h t ds 11h t alh t als d in 8639 3 continues to 3 of next page pa16 to 19 ca0 to 7 ca0 to 7 ca8 to 13 pa0 to 7 pa8 to 15 page address m+n district-0 2 t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 23 multi-page program operation with data cache timing diagram (4/4) (note) make sure to terminate the operation with 80h-10h command sequence. if the operation is terminated by 80h-15h command sequence, monitor i/o 6 (ready / busy) by issuing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operation. ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is t prog max. 71h t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 3 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 8639 continued from 3 of last page 80h ca0 to 7 ca8 to 13 pa0 to 7 pa8 to 15 pa16 to 19 d in 1 10h status d in 0 page address m+n district-1 status t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 24 auto block erase timing diagram t cs 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read command erase start command status output t alh pa16 to 19 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 25 multi block erase timing diagram 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cs t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. d0h 71h t wb t berase busy status read command erase start command auto block erase setup command i/o1 to status output t alh repeat 2 times (district-0,1) pa16 to 19 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 26 id read operation timing diagram : v ih or v il we cle re t cr ce ale i/o t ar id read command address 00 maker code device code t rea t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea d7h t rea t rea see table 5 see table 5 t rea see table 5 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 27 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by / ry = l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate th e operating condition of the device. the by / ry signal is in busy state ( by / ry = l) during the program, erase and read operations and will return to ready state ( by / ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vcc with an appropriate resister. power on select: psl the psl signal is used to select wh ether the device initialization should take place during the device power on or during the first reset. please refer to the application note (2) for details. ce we re wp by / ry free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 28 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 8640 bytes in which 8192 bytes are used for main memory storage and 448 bytes are for redundancy or for other uses. 1 page = 8640 bytes 1 block = 8640 bytes 128 pages = (1m + 56k) bytes capacity = 8640 bytes 128pages 4100 blocks table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l ca13 ca12 ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca13: column address pa0 to pa19: page address pa7 to pa19: block address pa0 to pa6: nand address in block fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 fifth cycle l l l l pa19 pa18 pa17 pa16 8640 524800 pages 4100 blocks 8192 8192 448 448 page buffe r data cache i/o8 i/o1 128 pages = 1 block 8i/o free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 29 extended blocks arrangement the device has 4 extended blocks to increase valid bloc ks. extended blocks can be accessed by the following addressing. main blocks (4096blocks) extended blocks (4 blocks) block 0 (district 0) block 1 (district 1) block 4095 (district 1) block 4094 (district 0) block 4098 (district 0) 00000h 00080h 7ff80h page address (pa0-19) 7ff00h 80100h block 2 (district 0) block 3 (district 1) 00280h block 4096 (district 0) block 4097 (district 1) 80000h 80080h block 4 (district 0) block 5 (district 1) block 4099 (district 1) 00200h 00100h 00180h 80180h free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 30 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, comma nd input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 psl * 3 command input h l l h * 0v/ v cc/ nu data input l l l h h 0v/ v cc/ nu address input l h l h * 0v/ v cc/ nu serial data output l l l h * 0v/ v cc/ nu during program (busy) * * * * * h 0v/ v cc/ nu during erase (busy) * * * * * h 0v/ v cc/ nu * * h * * * 0v/ v cc/ nu during read (busy) * * l h ( * 2) h ( * 2) * 0v/ v cc/ nu program, erase inhibit * * * * * l 0v/ v cc/ nu standby * * h * * 0 v/v cc 0v/ v cc/ nu h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended command/address input to the device or read to device. reset or status read command can be input during read busy. * 3: psl must be tied to either 0v or vcc, or left unconnected (nu). free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 31 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 ? read 00 30 column address change in serial data output 05 e0 read with data cache 31 ? read start for last page in read cycle with data cache 3f ? auto page program 80 10 column address change in serial data input 85 ? auto program with data cache 80 15 multi page program 80 11 read for page copy (2) 00 3a auto program with data cache during page copy (2) 8c 15 auto program for last page during page copy (2) 8c 10 auto block erase 60 d0 id read 90 ? status read 70 ? { status read for multi-page program or multi block erase 71 ? { reset ff ? { table 4 shows the operation states fo r read mode, when treh is long. table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8 765432i/o1 serial data input: 80h free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 32 device operation read mode read mode is set when the "00h" and ?30h? commands are issued to th e command register. between the two commands, a start address for the read mode needs to be issued. refer to the figures below for the sequence and the block diagram (refer to the detailed timing chart.). random column address change in read cycle by / ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start-address input a data transfer operation from the cell array to the data cache via page buffer starts on the rising edge of we in the 30h command input cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. cell array select page n m m data cache page buffer i/o1 to 8: m = 8639 start-address input select page n m by / ry we cle 00h ce ale i/o col. m page n m? busy page n 30h 05h e0h col. m? m m + 1 m? m? + 1 m? + 2m? + 3m? + 4 page n col. m start from col. m start from col. m? during the serial data output from the data cache, the column address can be changed by inputting a new column address using the 05h and e0h commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. t r m + 2m + 3 re free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 33 read operation with read cache the device has a read operation with data cache that enables the high speed read oper ation shown below. when the block address changes, this sequence has to be started from the beginning. page n + 2 if the 31h command is issued to the device, the data content of the next page is transferred to the page buffer during serial d ata out from the data cache, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1 normal read. data is transferred from page n to data cache th rough page buffer. during this time period, the device outputs b usy state for tr max. 2 after the ready/busy returns to ready, 31h command is issued a nd data is transferred to data cache from page buffer again. th is data transfer takes tdcbsyr1 max and the completion of this time period can be detected by ready/busy signal. 3 data of page n + 1 is transferred to page buffer from cell while the data of p age n in data cache can be read out by /re clock simultaneously. 4 the 31h command makes data of page n + 1 transfer to data cache from page buffer after the completion of the transfer from cell to page buffer. the device outputs bu sy state for tdcbsyr1 max.. this busy period depends on the combination of the internal dat a transfer time from cell to page buffer and the serial data out time. 5 data of page n + 2 is transferred to page buffer from cell while the data of page n + 1 in data cache can be read out by /re clock simultaneously 6 the 3fh command makes the data of page n + 2 transfer to the data cache from the page buffer after the completion of the transfer from cell to page buffer. the device ou tputs busy state for tdcbsyr1 max.. this busy period depends on the combination of t he internal data transfer time from cell to page buffer and the serial data out time. 7 data of page n + 2 in data cache can be read out, but since the 3fh command does not transfer the data from the memory cell to page buffer, the device can accept new command input immediately after the completion of serial data out. by / ry we cle 00h ce ale i/o t r 30h col. m page n 0 1 23 31h 31h 0 1 23 page address n column 0 8639 page address n + 1 8639 0 1 23 page address n + 2 8639 3fh data cache page buffer cell array 1 2 3 3 4 5 5 1 6 7 page n page n page n + 1 page n 30h 31h & re clock page n + 1 page n + 2 page n + 1 31h & re clock page n + 2 3fh & re clock 1 2 4 3 5 6 7 t dcbsyr1 t dcbsyr1 t dcbsyr1 re free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 34 multi page read operation the device has a multi page read operation and multi page read with data cache operation.. (1) multi page read without data cache the sequence of command and a ddress input is shown below. same page address (pa0 to pa6) within each district has to be selected. the data transfer operation from the cell array to th e data cache via page buffer starts on the rising edge of we in the 30h command input cycle (after the 2 districts address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to re ady state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. selected page reading district 0 district 1 selected page by / ry 60 command input page address pa0 to pa19 (district 0) tr address input 60 page address pa0 to pa19 (district 1) address input 30 a a by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (district 0) address input 05 column address ca0 to ca13 (district 0) address input e0 b b a a data output by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (district 1) address input 05 column address ca0 to ca13 (district 1) address input e0 b b data output (district 0) (district 1) free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 35 (2) multi page read with data cache when the block address changes (increments) this sequenced has to be started from the beginning. the sequence of command and a ddress input is shown below. same page address (pa0 to pa6) within each district has to be selected. by / ry 60 command input page address pa0 to pa19 (page m0 ; district 0) tr address input 60 page address pa0 to pa19 (page n0 ; district 1) address input 30 a a by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (page m0 ; district 0) address input 05 column address ca0 to ca13 (district 0) address input e0 b a a data output by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (page n0 ; district 1) address input 05 column address ca0 to ca13 (district 1) address input e0 b b data output (district 0) (district 1) 31 c c by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (page m127 ; district 0) address input 05 column address ca0 to ca13 (district 0) address input e0 d c c data output by / ry 00 command input column + page address ca0 to ca13, pa0 to pa19 (page n127 ; district 1) address input 05 column address ca0 to ca13 (district 1) address input e0 d d data output (district 0) (district 1) 3f b return to a re p eat a max of 127 times tdcbsyr1 tdcbsyr1 d free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 36 (3) notes (a) internal addressing in relation with the districts to use multi page read operation, the internal addressing should be considered in relation with the district. ? the device consists from 2 districts. ? each district consists from 2050 erase blocks. ? the allocation rule is follows. district 0: block 0, block 2, block 4, block 6,, block 4098 district 1: block 1, block 3, block 5, block 7,, block 4099 (b) address input restriction for the multi page read operation there are following restrictions in using multi page read; (restriction) maximum one block should be se lected from each district. same page address (pa0 to pa6) within two districts has to be selected. for example; (60) [district 0, page address 0x00000] (6 0) [district 1, page address 0x00080] (30) (60) [district 0, page address 0x00001] (6 0) [district 1, page address 0x00081] (30) (acceptance) there is no order limitation of th e district for the address input. for example, following operation is accepted; (60) [district 0] (60) [district 1] (30) (60) [district 1] (60) [district 0] (30) it requires no mutual address relation betw een the selected blocks from each district. (c) wp signal make sure wp is held to high level when multi page read operation is performed free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 37 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, addr ess and data input is shown below. (refer to the detailed timing chart.) the data is transferred (programmed) from the data cache via the page buffer to the selected page on the rising edge of we following input of the ?10h? command. after programming, the programmed data is transferred back to the page buffer to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification cle 80h ale i/o page p ce we col. m din 10h 70h din din din data status out re by ry/ free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 38 random column address change in auto page program operation the column address can be changed by the 85h command during the data input sequ ence of the auto page program operation. two address input cycles after the 85h command are reco gnized as a new column address for the data input. after the new data is input to the new column address, the 10h command initia tes the actual data program into the selected page automatically. the random column address change operation can be repeated multiple times within the same page. twhw is the time from the the we rising edge of final address cycle to the we falling edge of first data cycle. we high hold time for the final address input after 85h co mmand is also needed more time (twhw) than twh. 80h page n col. m 85h din din 10h status din din din din col. m? din din 70h busy data input selected page readin g & verification program col. m col. m? cle 85h ale i/o we col. m? din din din t wh t whw free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 39 auto page program operation with data cache the device has an auto page program with data cache operation enabling the high speed program operat ion shown below. when the b lock address changes this sequenced has to be started from the beginning. by / ry cle ale i/o ce we page n 80h a dd a dd a dd a dd status output din 15h 70h din din page n + 1 80h a dd a dd a dd a dd 1 status output din 15h 70h din din page n + p 80h a dd a dd a dd a dd 3 4 status output din 10h 70h din din 5 6 data cache page buffer cell array page n + p 1 2 3 4 5 5 6 page n page n + 1 data for page n + p 3 a dd a dd a dd data for page n data for page n data for page n + 1 data for page n + 1 page n + p ? 1 t dcbsyw2 t dcbsyw2 t prog (note) issuing the 15h command to the device after serial data i nput initiates the program operation with data cache 1 data for page n is input to data cache. 2 data is transferred to the page buffer by the 15h command. during the transfer the ready/busy outputs busy state (t dcbsyw2 ). 3 data is programmed to the selected page while the data for page n + 1 is input to the data cache. 4 by the 15h command, the data in the data cache is transferred to the page buffer after the programming of page n is completed . the device output busy state from the 15h command until the data cache becomes empty. the duration of this perio d depends on timing between the internal programming of page n an d serial data input for page n + 1 (t dcbsyw2 ). 5 data for page n + p is input to the data cache while the data of the page n + p ? 1 is being programmed. 6 the programming with data cache is terminated by the 10h command. when the device becomes ready, it shows that the internal p rogramming of the page n + p is completed. note: since the last page programming by the 10h command is initia ted after the previous cache program, the tprog during cache programming is given by the following; t prog = t prog for the last page + t prog of the previous page ? ( command input cycle + address input cycle + data input cycle time of the last page) re 2 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 40 pass/fail status for each page programmed by the auto page programming with data cache operation can be detected by the status read operation. z i/o1 : pass/fail of the curr ent page program operation. z i/o2 : pass/fail of the previous page program operation. the pass/fail status on i/o1 and i/o2 ar e valid under the following conditions. z status on i/o1: page buffer ready/busy is ready state. the page buffer ready/busy is output on i/o6 by status read operation or by / ry pin after the 10h command z status on i/o2: data cache read/busy is ready state. the data cache ready/busy is output on i/o7 by status read operation or by / ry pin after the 15h command. 80h?15h 70h status out page 1 data cache busy page buffer busy page 1 page 2 70h 70h page 2 70h 80h?15h page n ? 1 80h?10h page n page n ? 1 page n 70h 80h?15h i/o2 => i/o1 => invalid invalid page 1 invalid page n ? 2 invalid invalid invalid page n ? 1 page n page 1 page 2 70h if the page buffer busy returns to ready before the next 80h command input, and if status read is done during this ready period, the status read provides pass/fail fo r page 2 on i/o1 and pass/fail result for page1 on i/o2 status out status out status out status out status out example) by ry/ pin free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 41 multi page program with data cache the device has a multi page program with data cache operation, which enables ev en higher speed program operation compared to auto page program with data cache as shown below. when the block address changes (increments) this sequenced has to be started from the beginning. the sequence of command, address an d data input is shown below. (refer to the detailed timing chart.) after ?15h? or ?10h? program command is input to device , physical programing star ts as follows. for details of auto program with data cache, refer to ?auto page progra m with data cache?. by / ry data input command data input 0 to 8639 15 80 80 11 10 80 80 11 data input command address input (district 0) data input 0 to 8639 dummy program command data input command data input 0 to 8639 data input command data input 0 to 8639 address input (district 1) program with data cache command address input (district 0) dummy program command address input (district 1) auto page program command the data is transferred (programmed) from the page buffer to the selected page on the rising edge o f -we following input of the ?15h? or ?10h? command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does no t succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page reading & verification program district 0 district 1 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 42 starting the above operation from 1s t page of the selected erase blocks , and then repeating the operation total 128 times with incrementing the page address in the blocks, and then input the last page data of the blocks, ?10h? command executes fi nal programming. make sure to terminated with 80h-10h command sequence. in this full sequence, the co mmand sequence is following. after the ?15h? or ?10h? command, the results of the above operation is shown through the ?71h?status read command. the 71h command status description is as below. status output i/o1 chip status1 : pass/fail pass: 0 fail: 1 i/o2 district 0 chip status1 : pass/fail pass: 0 fail: 1 i/o3 district 1 chip status1 : pass/fail pass: 0 fail: 1 i/o4 district 0 chip status2 : pass/fail pass: 0 fail: 1 i/o5 district 1 chip status2 : pass/fail pass: 0 fail: 1 i/o6 ready/busy ready: 1 busy: 0 i/o7 data cache ready/busy ready: 1 busy: 0 i/o8 write protect protect: 0 not protect: 1 i/o1 describes pass/fail condition of district 0 and 1(or data of i/o2 and i/o3). if one of the districts fails during multi page program operation, it shows ?fail?. i/o2 to 5 shows the pass/fail condition of each district. for details on ?chip status1? and ?chip status2?, refer to section ?status read?. 10 or15 71 pass i/o status read command fail by / ry 15 15 10 15 80 80 80 80 11 11 11 11 80 80 80 80 1st 127th 128th free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 43 internal addressing in relation with the districts to use multi page program operation, the internal addressing should be considered in relation with the district. ? the device consists from 2 districts. ? each district consists from 2050 erase blocks. ? the allocation rule is follows. district 0: block 0, block 2, block 4, block 6,, block 4098 district 1: block 1, block 3, block 5, block 7,, block 4099 address input restriction for the multi page program with data cache operation there are following restrictions in usin g multi page program with data cache; (restriction) maximum one block should be se lected from each district. same page address (pa0 to pa6) within two districts has to be selected. for example; (80) [district 0, page address 0x00000] (11) (80) [district 1, page address 0x00080] (15 or 10) (80) [district 0, page address 0x00001] (11) (80) [district 1, page address 0x00081] (15 or 10) (acceptance) there is no order limitation of th e district for the address input. for example, following operation is accepted; (80) [district 0] (11) (80) [district 1] (15 or 10) (80) [district 1] (11) (80) [district 0] (15 or 10) it requires no mutual address relation betw een the selected blocks from each district. operating restriction during the multi page program with data cache operation (restriction) the operation has to be terminated with ?10h? command. once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for status read command and rese t command. if ff reset command is input before write operation to page b is complete, it may cause damage to data not only to the programmed page, but also to the adjacent page a. regardins page a and b, please see below table. page a page b page a page b 0 2 1 4 3 6 5 8 97 100 7 10 99 102 9 12 101 104 11 14 103 106 13 16 105 108 15 18 107 110 17 20 109 112 19 22 111 114 21 24 113 116 23 26 115 118 25 28 117 120 27 30 119 122 121 124 123 126 125 127 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 44 page copy (2) by using page copy (2), data in a page can be copied to another page after the data has been read out. when the block address changes (increments) this sequenced has to be started from the beginning. page copy (2) operation is as following. 1 data for page n is transferred to the data cache. 2 data for page n is read out. 3 copy page address m is input and if the data needs to be changed, changed data is input. 4 data cache for page m is transferred to the page buffer. 5 after the ready state, data for page n + p1 is output from the data cache while the data of page m is being programmed. when changing data, changed data is input. 1 3 4 5 2 t r t dcbsyw2 t dcbsyr2 by ry/ 00 command input address ca0 to ca13, pa0 to pa19 (page n) address input 30 address input 8c a data intput 15 00 address input 3a data output address ca0 to ca13, pa0 to pa19 (page m) address ca0 to ca13, pa0 to pa19 (page n+p1) a data output col = 0 start col = 0 start data cache page buffer cell array 1 2 3 4 5 page n data for page n data for page n page m page n + p1 data for page n + p1 data for page m free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 45 6 copy page address (m + r1) is input and if the data needs to be changed, changed data is input. 7 after programming of page m is completed, data cache for page m + r1 is transferred to the page buffer. 8 by the 15h command, the data in the page buffer is programmed to page m + r1. data for page n + p2 is transferred to the data cache. 9 the data in the page buffer is programmed to page m + rn ? 1. data for page n + pn is transferred to the data cache. by / ry 8 9 6 7 t dcbsyw2 t dcbsyr2 t dcbsyr2 when changing data, changed data is input. command input address ca0 to ca13, pa0 to pa19 (page m+r1) b 00 address input 3a data output address input 8c data intput 15 00 address input 3a data output address ca0 to ca13, pa0 to pa19 (page n+p2) address ca0 to ca13, pa0 to pa19 (page n+pn) a b a col = 0 start col = 0 start data cache page buffer cell array 6 7 8 page m data for page m + r1 data for pa g e m + + p2 data for page n + pn 9 page m + r1 page n + p2 page n + p1 page m + rn ? 1 page n + pn page m + rn ? 1 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 46 10 copy page address (m + rn) is input and if the data needs to be changed, changed data is input. 11 by issuing the 10h command, the data in the page buffer is programmed to page m + rn. (*1) since the last page programming by the 10h command is initiated after the previous cache program, the t prog here will be expected as the following, t prog = t prog of the last page + tprog of the previous page ? ( command input cycle + address input cycle + data output/input cycle time of the last page) note) this operation needs to be executed within each district. data input is required only if previous data output needs to be altered. if the data has to be changed, locate the desired address with the column and page address input after the 8ch command, and cha nge only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. make sure wp is held to high level when page copy (2) operation is performed. also make sure the page copy operation is terminated with 8ch-10h command sequence data cache page buffer cell array page m + rn ? 1 data for page m + rn data for page m + rn page m + rn 10 11 by / ry 10 11 t prog (*1) command input address ca0 to ca13, pa0 to pa19 (page m+rn) address input 8c data intput 10 70 status output b b free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 47 multi page copy (2) by using multi page copy (2), data in two pages can be copied to another pa ges after the data has been read out. when the each block addre ss changes (increments) this sequenced has to be started from the beginning. same page address (pa0 to pa6) within two districts has to be selected. t r by ry/ 60 command input address pa0 to pa19 (page m0 ; district 0) address input 30 a 00 address input e0 data output address ca0 to ca13, pa0 to pa19 (page m0) a 60 address input address pa0 to pa19 (page n0 ; district 1) 05 address input address ca0 to ca13 (col = 0) t dcbsyw1 00 address input 05 address input e0 b b data output address ca0 to ca13, pa0 to pa19 (page n0) address ca0 to ca13 (col = 0) 8c address input 11 data input address ca0 to ca13, pa0 to pa19 (page m0 ; district 0) by ry/ a a 00 address input 05 address input e0 data output address ca0 to ca13, pa0 to pa19 (page m1) address ca0 to ca13 (col = 0) by ry/ 00 address input 05 address input e0 data output address ca0 to ca13, pa0 to pa19 (page n1) address ca0 to ca13 (col = 0) d d c c t dcbsyw2 8c address input 15 data input address ca0 to ca13, pa0 to pa19 (page n0 ; district 1) by ry/ 60 address pa0 to pa19 (page m1 ; district 0) address input 3a 60 address input address pa0 to pa19 (page n1 ; district 1) c c b b t dcbsyr2 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 48 t dcbsyw1 00 address input 05 address input e0 g g data output address ca0 to ca13, pa0 to pa19 (page n127) address ca0 to ca13 (col = 0) 8c address input 11 data input address ca0 to ca13, pa0 to pa19 (page m127 ; district 0) by ry/ f f t dcbsyr2 by ry/ 60 address pa0 to pa19 (page m127 ; district 0) address input 3a f 00 address input e0 data output address ca0 to ca13, pa0 to pa19 (page m127) f 60 address input address pa0 to pa19 (page n127 ; district 1) 05 address input address ca0 to ca13 (col = 0) e e t dcbsyw1 8c address input 11 data input address ca0 to ca13, pa0 to pa19 (page m1 ; district 0) by ry/ e e d d 8c address input 15 data input address ca0 to ca13, pa0 to pa19 (page n1 ; district 1) t dcbsyw2 by ry/ g g 8c address input 10 data input address ca0 to ca13, pa0 to pa19 (page n127 ; district 1) tprog ( *1 ) note) this operation needs to be ex ecuted within each district. data input is required only if previ ous data output needs to be altered. if the data has to be changed, locate the desired addr ess with the column and page address input after the 8ch command, and change only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. make sure wp is held to high level when multi page copy (2) operation is performed. also make sure the multi page copy operation is terminated with 8ch-10h command sequence ( * 1) t prog : since the last page programming by 10h comm and is initiated after the previous cache program, the t prog* during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page-a a = (command input cycle + address input cycle + data output/input cycle time of the last page) if ?a? exceeds the t prog of previous page, t prog of the last page is t prog max. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 49 auto block erase the auto block erase operation st arts on the rising edge of we after the erase start command ?d0h? which follows the erase setup command ?60h?. this two-cycle process for erase oper ations acts as an extra layer of protection from accidental erasure of data due to external noise. the de vice automatically executes the erase and verify operations. multi block erase the multi block erase operation starts by selecting two block addresses before d0h command as in below diagram. the device automatically executes the erase and verify operations and the result can be monitored by checking the status by 71h status read command. for details on 71h status read command, refer to section ?multi page program with data cache?. internal addressing in relation with the districts to use multi block erase operation, the internal addressing should be consider ed in relation with the district. ? the device consists from 2 districts. ? each district consists from 2050 erase blocks. ? the allocation rule is follows. district 0: block 0, block 2, block 4, block 6,, block 4094, block 4096, block 4098 district 1: block 1, block 3, block 5, block 7,, block 4095, block 4097, block 4099 address input restriction for the multi block erase there are following restrictions in using multi block erase (restriction) maximum one block should be se lected from each district. for example; (60) [district 0] (60) [district 1] (d0) (acceptance) there is no order limitation of th e district for the address input. for example, following operation is accepted; (60) [district 1] (60) [district 0] (d0) it requires no mutual address relation betw een the selected blocks from each district. make sure to terminate the operation with d0h command. if the operation needs to be terminated before d0h command input, input the ffh reset co mmand to terminate the operation. pass i/o fail by / ry 60 d0 70 block address input: 3 cycles status read command busy erase start command pass i/o fail by / ry 60 d0 71 block address input: 3 cycles district 0 status read command busy erase start command 60 block address input: 3 cycles district 1 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 50 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 0 1 0 1 1 1 d7h 3rd data chip number, cell type ? ? ? ? ? ? ? ? see table 4th data page size, block size ? ? ? ? ? ? ? ? see table 5th data plane number ? ? ? ? ? ? ? ? see table 3rd data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 90h 00h 98h d7h see table 5 see table 5 we cle re t cr ce ale i/o t ar t rea id read command address 00 maker code device code see table 5 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 51 4th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 2 kb 4 kb 8 kb reserved 0 0 1 1 0 1 0 1 block size (without redundant area) 128 kb 256 kb 512 kb 1 mb reserved 0 0 0 0 1 0 0 1 1 0 or 1 0 1 0 1 0 or 1 5th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number 1 plane 2 plane 4 plane 8 plane 0 0 1 1 0 1 0 1 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 52 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/ busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using re after a ?70h? command input. the status read can also be used during a read operation to find out the ready/busy status. the resulting information is outlined in table 6. table 6. status output table definition page program block erase cache program read cache read i/o1 chip status1 pass: 0 fail: 1 pass/fail pass/fail invalid i/o2 chip status 2 pass: 0 fail: 1 invalid pass/fail invalid i/o3 not used 0 0 0 i/o4 not used 0 0 0 i/o5 not used 0 0 0 i/o6 page buffer ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o7 data cache ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o8 write protect not protected :1 protected: 0 write protect write protect write protect the pass/fail status on i/o1 and i/o2 is only valid during a program/erase operation when the device is in the ready state. chip status 1: during a auto page program or auto block erase operation this bit indicates the pass/fail result. during a auto page programming with data cache op eration, this bit shows the pass/fail results of the current page program operation, and therefore this bit is only valid when i/o6 shows the ready state. chip status 2: this bit shows the pass/fail result of the previous page program operat ion during auto page programming with data cache. this status is va lid when i/o7 shows the ready state. the status output on the i/o6 is th e same as that of i/o7 if the comma nd input just before the 70h is not 15h or 31h. free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 53 an application example with multiple de vices is shown in the figure below. system design note: if the by / ry pin signals from multiple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. reset the reset mode stops all operations. for example, in ca se of a program or erase operation, the internally generated voltage is discharged to 0 volt and the device enters the wait state. reset during a cache program/page copy may not just stop the most recent page program but it may also stop the previous program to a page de pending on when the ff reset is input. the response to a ?ffh? reset co mmand input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 by / ry t rst (max 30 s) device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n + 1 1 n ce + ale we re by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n by / ry cle n ce busy i/o1 to i/o8 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 54 when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail pass : ready/busy ready ff 70 by / ry 00 ff 00 by / ry t rst (max 10 s) 30 internal erase voltage d0 ff 00 by / ry t rst (max 500 s) 00 by / ry t rst (max 10 s) ff free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 55 application notes and comments (1) power-on/off sequence: the timing sequence shown in the figure below is necessary for the power-on/off sequence. the device internal initialization starts after the po wer supply reaches an appropriate level in the power on sequence. during the initialization the device ready/busy signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h(71h). the wp signal is useful for protecting against data corruption at power-on/off. (2) power-on reset the device goes into automatic self initialization du ring power on if psl is tied either to gnd or nu. during the initialization pr ocess, the device consumes a maximum current of 30 ma (i cco0 ). if psl is tied to vcc, the device will not complete its self init ialization during power on and will not consume i cco0 , and completes the initialization process with the first re set command input after power on. during the first ffh reset busy period, the device consumes a maximum current of 30 ma (i cco0 ). in either case (psl = gnd/ nu or v cc ), the following sequence is necessary because so me input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in t able 3. input of a command other th an those specified in table 3 is prohibited. stored data may be co rrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not input any command except 70h(71h) and ffh. ff reset power on v il operation 0 v v cc 2.7 v 2.5 v v il don?t care don?t care v ih ce , we , re wp cle, ale invalid don?t care ready/busy 5 ms max 100 s max don?t care invalid 5 ms max 100 s max 1ms 2.7 v 2.5 v 0.5 v 0.5 v free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 56 (5) acceptable commands after serial input command ?80h? once the serial input command ?80h ? has been input, do not input an y command other than the column address change in serial data input command ?85h?, auto program command ?10h?, multi page program command ?11h?, auto program with data cache command ?15h?, or the reset command ?ffh?. if a command other than ?85h?, ? 10h? , ?11h? , ?15h? or ?ffh? is in put, the program operation is not performed and the device operation is set to the mode which the input command specifies. (6) addressing for program operation within a block, the pages must be programmed consecut ively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the bl ock. random page address programming is prohibited. command other than ?85h?, ?10h?, ?11h? , ?15h? or ?ffh? 80 programming cannot be executed. 10 xx mode specified by the command. we by / ry 80 ff address input data in: data (1) page 0 data register page 2 page 1 page 31 page 127 (1) (2) (3) (32) (128) data (128) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 127 (2) (32) (3) (1) (128) data (128) ex.) random page program (prohibition) free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 57 (7) status read during a read operation the device status can be read out by inputting the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h ? command, the device will not return to read mode unless the read command ?00h? is input during [a]. if the read command ?00h? is input during [a], status read mode is reset, and the device returns to read mode . in this case, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) by / ry : termination for the ready/busy pin ( by / ry ) a pull-up resistor needs to be used for termination because the by / ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by / ry c l 1.5 s 1.0 s 0.5 s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc = 3.3 v ta = 25c c l = 50 pf t f ready v cc 1.0 v t r 3.0 v 1.0 v busy 00 address n command ce we by / ry re [a] status read command input status read status output . 70 00 30 free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 58 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 59 (11) when six address cycles are input although the device may read in a sixth address, it is ignored inside the chip. read operation program operation (12) several programming cycles on the same page (partial page program) this device does not support partial page programming. cle address input 00h ce we ale i/o by / ry ignored 30h cle ce we ale i/o address input ignored 80h data input free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 60 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, the bad bl ock information is marked on each bad block. please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over th e device lifetime is as follows: min typ. max unit valid (good) block number 3936 ? 4100 block bad block test flow regarding invalid blocks, bad block mark is in either the 1st or the last page. * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read ffh check column 0 or 8192 of the first page start fail block no = 1 block no. = block no. + 1 last block end yes no read ffh check column 0 or 8192 of the last page entry bad block *1 pass fail free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 61 (14) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase block replacement page programming failure status read after program block replacement random bit programming failure ?1 to 0? ecc ? ecc: error correction code. 24 bit co rrection per 1kbyte s is necessary. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. (16) if ff reset command is input before completion of writ e operation to page b, it may cause damage to data not only to the programmed page, but al so to the adjacent page a. regard ing page a and b, please see page 42. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 62 (17) reliability guidance this reliability guidance is intended to notify so me guidance related to using mlc nand flash with 24bit ecc for each 1024 bytes. for detailed reliability data, please refer to toshiba?s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a progra m status failure or erase st atus failure is detected. the other failure modes may be recovered by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. ? write/erase endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto program or au to block erase operation. the cumula tive bad block count will increase along with the number of write/erase cycles. ? data retention the data in memory may change after a certain amount of storage time. this is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristics image of write/erase endurance and data retention. ? read disturb a read operation may disturb the data in memory. th e data may change due to charge gain. usually, bit errors occur on other pages in the block, not the page being read. after a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. after block erasure and reprogramming, the block may become usable again. write/erase endurance [cycles] data retention [years] free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 63 package dimensions weight: tbd g (typ.) free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 64 revision history date rev. description 2009-01-15 1.00 original version 2009-03-25 1.10 to add the extended block( page 1,4,28,29,49,60 ) to separate twhr timing to twhr1 and twhr2( page 5,9,14 ) to change iccs spec from 50ua to 100ua( page 1, 4 ) to modify power off/on sequence( page 55 ) free datasheet http:///
toshiba confidential TC58NVG5D2FTA00 rev 1.1 2009-03-25c 65 restrictions on product use ?toshiba corporation, and its subsidia ries and affiliates (colle ctively "toshiba"), rese rve the right to make changes to the information in this document, and re lated hardware, software and systems (collectively "product") without notice. ?this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ?though toshiba works continually to improve product' s quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems wh ich minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before creating an d producing designs and using, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application that product will be used wi th or for. customers are solely responsible for all aspects of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such de sign or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced do cuments; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ?product is intended for use in general electronics applic ations (e.g., computers, personal equipment, office equipment, measuring equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document. pr oduct is neither intended nor warranted for use in equipment or systems that require ex traordinarily high levels of qualit y and/or reliability and/or a malfunction or failure of which may cause loss of human life, bod ily injury, serious property damage or serious public impact ("unintended use"). unintended use includes, wit hout limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, dev ices related to electric power, and equipment used in finance-related fields. do not use product for un intended use unless specifically permitted in this document. ?do not disassemble, analyze, reverse-engineer, alter, m odify, translate or copy product, whether in whole or in part. ?product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ?the information contained herein is presented only as guidance for pr oduct use. no responsibility is assumed by toshiba for any infringement of patents or any other intellectual prope rty rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or impli ed, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liabil ity whatsoever, including wi thout limitation, indirect, consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of oppo rtunities, business in terruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ?do not use or otherwise make available product or rela ted software or technology for any military purposes, including without limitation, for the design, development, use, stoc kpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. export administration regulat ions. export and re-export of product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. ?please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of product. please use product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled su bstances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or lo sses occurring as a result of noncompliance with applicable laws and regulations. free datasheet http:///

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